MAXVY Announces SPD5 HUB Controller IP – Silicon Proven with Multiple Customers and Validated Across Leading DIMM Vendors

Bangalore, India – 05-11-2026

MAXVY Technologies Pvt. Ltd. proudly announces that its SPD5 HUB Controller IP has achieved multiple customer silicon success and has been validated with a wide range of DDR5 DIMM vendors, demonstrating exceptional interoperability, reliability, and performance in real-world silicon implementations.

The MAXVY SPD5 HUB Controller IP is fully compliant with JEDEC DDR5 SPD5 specifications and provides a robust, feature-rich solution designed to meet the growing demands of high-speed DDR5 memory systems. Its optimized architecture ensures seamless integration and superior performance across diverse DIMM configurations.

“Achieving silicon-proven success across multiple customer platforms and validation with leading DIMM vendors is a testament to MAXVY’s engineering excellence and commitment to quality,” said Founder and Managing Director of MAXVY Technologies Pvt. Ltd. “Our SPD5 HUB Controller IP empowers customers with a reliable and flexible solution designed for next-generation DDR5 memory systems.”

This milestone underscores MAXVY’s commitment to delivering high-quality, silicon-proven IP solutions that enable next-generation system designs and strengthen customer success in the global semiconductor ecosystem.

Key Highlights

  • Multiple customer silicon-proven results
  • Validated with various DIMM vendors
  • Fully compliant with JEDEC SPD5 specifications
  • Optimized for DDR5 memory systems

Key Features

  • Compliance as per JEDEC’s JESD300-5
  • Dynamic Address Assignment
  • Common Command Codes (CCCs)
  • Specified 1.2V–3.3V Operation for 50pf C load
  • Target Reset
  • Error Detection and Recovery
  • 12.5 MHz SDR (Controller, Target, and Legacy I2C Target Compatibility)
  • Legacy compatibility with I2C (I3C and I2C devices can coexist on the same bus)
  • In-Band Interrupt (w/MDB)
  • Interrupt Arbitration
  • Set Static Address as Dynamic Address CCC (SETAASA)
  • Synchronous Timing Control
  • SPD5 Command Support:
    • NVM memory
    • Register Space
    • NVM memory Write and Read access
    • Offline Tester operation supported

Comprehensive IP Portfolio

MAXVY’s IP portfolio extends beyond the SPD5 HUB Controller to include a diverse range of Controller and Verification IP solutions:

  • Controller IPs supporting both Manager and Peripheral roles, offering flexible data and control transport with precise synchronization for complex system architectures.
  • Verification IPs providing comprehensive protocol coverage with configurable timing parameters and advanced corner-case validation to ensure design robustness.
  • Extensive configurability and customization options with tailored deliverables, including FPGA prototyping and emulation platform support to accelerate validation and time-to-market.

About MAXVY

MAXVY Technologies Pvt. Ltd. is a leading semiconductor IP design company specializing in RTL Design, Verification IP, and IP Solutions for advanced SoC developments. With deep expertise in interface protocols and system-level design, MAXVY delivers high-performance, silicon-proven IP cores that accelerate time-to-market and enhance reliability for global semiconductor customers.

For more information contact [email protected]/[email protected].