MAXVY's provides configurable JESD204B TX/RX verification IP. JESD204B is a Serial Interface for Data Converters which are defined by JEDEC SOLID STATE TECHNOLOGY ASSOCIATION. Our VIP covers Transport and Data link layer functionality of JESD204B. MAXVY's VIP provides more flexible configuration to user to select their needs like lane,device configuration, data width.

Key Features

  • ADC - TX/RX DAC - TX/RX.
  • Support up to 12.5 Gbps data rate.
  • Support configurable device classification.
  • Support configurable subclass 0/1/2.
  • Support Frame alignment monitor and correction.
  • Support lane synchronization.
  • Support Lane alignment monitor and correction.
  • Support Link configuration.
  • Support Link re-initialization.
  • Support Deterministic Latency.
  • Support 8B/10B encode/decode.
  • Support Application specific control interface (user specific).

Block Diagram

jesd204b block-diagram


  • Configurable Option like lane,frame,TX/RX.
  • Supports both multi device configuration.
  • Simple steps to integrate into customer environment


  • Wireless Infrastructure Transceiver.
  • Software defined Radios.
  • Medical Imaging Systems.
  • Radar and Secure Communications


  • Basic Test Suite.
  • Random Testbench Environment.
  • Encrypted Source Code of VIP.
  • VIP user guide.
  • DataSheet / Evaluation
  • FAQ

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Frequently Asked Questions

1. What are the simulator and its versions in this VIP support?

Ans: It supports all the major SystemVerilog simulator like NC-SIM, Questasim, VCS, Aldec Riviera-pro.

2. Do you have any limitation on UVM library version?

Ans: It supports above UVM1.1 version. There is no limitation as of now.

3. Is it Possible to use in non-UVM testbench environment?

Ans: Yes. It can be possible.

4. Upon PO, how long does MAXVY be able to deliver the VIP along with License?

Ans: MAXVY deliver VIP after receiving PO, usually takes min 15days to maximum 30days.